IC Planarization

       The development of integrated circuits(IC), especially the exploration of ultralarge integrated circuits(ULSI) is essential to the fabrication of modern semiconductor devices, and thus is the basis of our information society. Owing to the excellent electron-transfer resistance and the low electrical resistance, the copper interconnects have been widely used in the IC fabrication, especially after the chemical mechanical polishing(CMP) was successfully introduced into the IC planarization. Additionally, unlike aluminum based metal interconnect systems which are formed by subtractive etch processes, copper interconnects are typically formed by damascene metal processes. Such processes are also sometimes referred to as inlaid metal processes. In a damascene process, trenches are formed in a first layer, and a metal layer is formed over the first layer including the trenches. Excess metal is then polished off, leaving individual interconnect lines in the trenches. The removal of excess copper is typically accomplished by chemical mechanical polishing and the CMP process seriously affects the reliability and yields of IC products. Presently, our research group is devoting ourselves to promoting the related IC-planarization techniques.

l         Researching subject：The chemical mechanical planarization of copper interconnects in IC & The Cu CMP slurry.

l         Potential Applications：The design and fabrication of ULSI.